Micro/Nano Device Reliability Laboratory
微纳器件可靠性研究室
Publications(2017~)

[1]      J. Wu, J. Chen (*), X. Jiang (*), “Atomistic Study ofLateral Charge Diffusion Degradation During Program/Erase Cycling in 3-D NANDFlash Memory”, IEEE Journal of the Electron Devices Society, vol.7,1,pp.626-631, 2019;

[2]     F. Wang, X. Ma, J. Wu,J. Chen(*), X. Jiang (*), “Atomistic Study of TransportCharacteristics in Sub-1nm Ultra-narrow Molybdenum Disulfide (MoS2) NanoribbonField Effect Transistors”, Silicon Nanoelectronics Workshop (SNW), Kyoto,Japan, June, 2019;

[3]     J. Wu, J. Chen(*), X. Jiang (*), “Excess Charge Effects on Semiconductor-metal PhaseTransition in Mono-layer MoTe2”, Silicon Nanoelectronics Workshop (SNW), Kyoto,Japan, June, 2019;

[4]     X. Zhan, C. Shen, Z. Ji (*), J. Chen (*),H. Fang, F. Guo and J. Zhang, “A Dual-Point technique for the entire ID-VGcharacterization into subthreshold region under Random Telegraph Noisecondition”, IEEE Electron Device Letter, vol.40, 5, pp.674-677, 2019;

[5]     R. Cao, J. Wu, W.Yang, J. Chen (*), X. Jiang (*), “Program/Erase Cycling EnhancedLateral Charge Diffusion in Triple-level Cell Charge-trapping 3D NAND FlashMemory”,IEEE International Reliability Physics Symposium (IRPS),Monterey, CA, USA, 2019;

[6]     X. Ma, Y. Liu, L. Wang,Y. En, J. Chen (*), X. Jiang (*), “Scaling behavior ofstate-to-state coupling during hole trapping at Si/SiO2”,IEEEInternational Reliability Physics Symposium (IRPS),Monterey, CA, USA, 2019;

[7]     J. Wu, X. Ma, J.Chen(*), X. Jiang(*), “Defects coupling impacts on mono-layer WSe2tunneling field-effect transistors”, Applied PhysicsExpress,12, 034001, 2019;

[8]     X. Zhan, M. Hou, F.Ma, Y. Su, J. Chen (*), H. Xu (*), “Room temperaturecrystallization of amorphous silicon film by ultrashort femtosecond laserpulses”, Optics and Laser Technology 112 (2019), pp.363-367;

[9]     X. Ma, Z. Fan, J. Wu,X. Jiang (*), J. Chen (*), “Computational Design of SiliconContacts on 2D Transition-Metal Dichalcogenides: The Roles of CrystallineOrientation, Doping Level, Passivation and Interfacial Layer”,IEDM Tech. Dig., San Francisco, CA, USA, p.24.2.1-24.2.4, 2018;

[10] J.Wang, Z. Ji, G. Yang, X. Chuai, F. Liu, Z. Zhou, C. Lu, W. Wei, X. Shi, J. Niu,L. Wang, H. Wang, J. Chen, Nianduan Lu, Chao Jiang (*), Ling Li (*)and M. Liu, “Charge Transfer within the F4 TCNQ-MoS2 van der Waals Interface:Toward Electrical Properties Tuning and Gas Sensing Application,” Adv. Funct.Mater. (2018) 1806244;

[11] X,Zhan, F. Ma, J. Chen (*), Y. Li and H. Xu (*),“Crystallizing amorphous silicon film by using femtosecond laser pulses,” 2018IEEE International Conference on Integrated Circuits, Technologies andApplications (ICTA), pp.84-85, November 21- 23, 2018, Beijing, China;

[12] W.Yang, Y. Li, B. Wang, H. Qian and J. Chen (*), “Positive BiasTemperature Instabilities in Vertical Gate-all-around poly-Si Nanowire Field-effectTransistor,” 2018 IEEE International Conference on Integrated Circuits,Technologies and Applications (ICTA), pp.175-176, November 21- 23, 2018,Beijing, China;

[13] J. Chen,“On the Reliability of Charge-Trap (CT) Type Three-dimensional (3D) NAND FlashMemory,” invited talk in The 14th International Conference on Solid-State andIntegrated Circuit Technology, October 31-November 3, 2018, Qingdao, China;

[14] R.Cao, J. Wu, W. Yang, Y. Li, J. Chen (*),“Error Bit Distributions in Triple-level Cell Three-dimensional (3D) NAND FlashMemory,” the 14th International Conference on Solid-State and IntegratedCircuit Technology (ICSICT), October 31- November 3, 2018, Qingdao, China;

[15] F.Ma, X. Zhan, Y. Li, J. Chen (*), “Numerical Simulations onNanosecond Pulse Laser Annealing in Vertical Polycrystalline Si MacaroniChannel,” the International Conference on Solid-State and Integrated CircuitTechnology (ICSICT), October 31- November 3, 2018, Qingdao, China;

[16] Z.Fan, J. Chen (*) and X. Jiang (*), “Electrical Contacts andTunable Rectifications in Monolayer GeSe-Metal Junctions,” Journal of PhysicsD: Appl. Phys. 51 (2018) 335104;

[17] J.Brown, R. Gao, J. Crowford, J. Wu, Z. Ji (*), J. Chen (*),J. Zhang, B. Zhou, B. Zhou, Q. Shi, W. Zhang, “A low-power and high-speed True RandomNumber Generator using generated RTN”,   Symposia on VLSITechnology, pp.95-96, Hawaii, USA, June, 2018;

[18] J.Wu, X. Ma, J. Chen (*), X. Jiang (*),“Se Vacancy Defects Coupling Effects in Mono-layer WSe2 Tunnel FETs”, SiliconNanoelectronics Workshop (SNW), Hawaii, USA, June, 2018;

[19] X.Ma, Z. Fan, J. Wu, J. Chen (*),X. Jiang (*), “Channel Bending Effects on On/Off Currents in Mono-Layer MoS2FETs”, Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, June, 2018;

[20] W.Yang, J. Zhao, H. Cao, S. Chiu, J. Chen (*),“Oxide-Nitride-Oxide(ONO) Inter-poly Dielectric (IPD) Scaling Impacts on DataRetention Characteristics in NAND Flash Memories”, Silicon NanoelectronicsWorkshop (SNW), Hawaii, USA, June, 2018;

[21] J.Lu, Z. Fan(*), J. Gong(*), J. Chen (*), H. ManduLa, Y. Zhang, S.Yang   and X. Jiang, Enhancementof tunneling current in monolayer phosphorene tunnel field effect transistorsby surface defects,Physical Chemistry Chemical Physics, 20,pp.5699~5707, 2018.

[22] J.Wu, Z. Fan, J. Chen (*),X. Jiang (*), “Atomic defects in monolayer WSe2 tunneling FETs studied bysystematic ab initio calculations,” Applied Physics Express,11, 054001, 2018

[23] X.Shi, G. Xu, X. Duan, N. Lu, J. Chen, L. Li, M. Liu, “Analyticalmodel of energy level alignment at metal-organic interface facilitating holeinjection,” International Conference on Simulation of Semiconductor Processesand Devices (SISPAD), pp.225-228, 2017.

[24] J.Wu, D. Han, W. Yang, S. Chen, X. Jiang (*), J. Chen(*), “Comprehensive Investigations on Charge DiffusionPhysics in SiN-based 3D NAND Flash Memory through Systematical Ab initioCalculations,” IEDM Tech. Dig.,San Francisco, CA, USA, p.4.5.1-4.5.4, 2017.

[25]   J.Chen, J. Wu, X.Jiang, “Impacts of Traps on Nano Scale Device Performance, Reliability, andNovel Applications”, invited talk, in International Microprocesses andNanotechnology Conference, JeJu, Korea, November, 2017;

[26]   J. Wu, Z. Fan, J. Chen (*), X. Jiang(*), “A Study on W Vacancy Defect in Mono-layer Transition-Metal Dichalcogenide(TMD) TFETs through Systematic Ab initio Calculations”, Silicon NanoelectronicsWorkshop (SNW), Kyoto, Japan, June, 2017;

[27]   H. Qiu, K. Takeuchi, T. Mizutani, T. Sarya, J.Chen, M. Kobayashi and T. Hitamoto. “Statistical Analyses of RandomTelegraph Noise (RTN) Amplitude in Ultra-Narrow (Deep Sub-10nm) SiliconNanowire Transistors,” in Symposia onVLSITechnology,Kyoto, Japan, June, 2017.