Micro/Nano Device Reliability Laboratory
微纳器件可靠性研究室
Publications(2017~)

[1] X, Zhan, F. Ma, J. Chen, Y. Li and H. Xu, “Crystallizing amorphoussilicon film by using femtosecond laser pulses,” 2018 IEEE InternationalConference on Integrated Circuits, Technologies and Applications (ICTA),November 21- November 23, 2018, Beijing, China;

[2] W. Yang, Y. Li, B.Wang, H. Qian and J. Chen, “Positive Bias Temperature Instabilities in VerticalGate-all-around poly-Si Nanowire Field-effect Transistor,” 2018 IEEEInternational Conference on Integrated Circuits, Technologies and Applications (ICTA),November 21- November 23, 2018, Beijing, China;

[3] J. Chen, “On the Reliability of Charge-Trap (CT) TypeThree-dimensional (3D) NAND Flash Memory,” invited talk in The 14th International Conference on Solid-State and Integrated Circuit Technology (ICSICT),October 31-November 3, 2018, Qingdao, China;

[4] R. Cao, J. Wu, W. Yang, Y. Li, J. Chen, “Error Bit Distributionsin Triple-level Cell Three-dimensional (3D) NAND Flash Memory,” the 14th International Conference on Solid-State and Integrated Circuit Technology(ICSICT), October 31- November 3, 2018, Qingdao, China;

[5] F. Ma, X. Zhan, Y. Li, J. Chen, “Numerical Simulations onNanosecond Pulse Laser Annealing in Vertical Polycrystalline Si Macaroni Channel,” the International Conference on Solid-State and Integrated CircuitTechnology (ICSICT), October 31- November 3, 2018, Qingdao, China;

[6] Z. Fan, J. Chen and X. Jiang, “Electrical Contacts and Tunable Rectifications in Monolayer GeSe-Metal Junctions,” Journal of Physics D:Applied Physics, 51, 335104, 2018;

[7] J. Brown, R. Gao, J. Crowford, J. Wu, Z. Ji, J. Chen, J. Zhang, B.Zhou, B. Zhou, Q. Shi, W. Zhang, “A low-power and high-speed True Random Number Generator using generated RTN”, Symposia on VLSI Technology, Hawaii, USA, June,2018;

[8] J. Wu, X. Ma, J. Chen, X. Jiang, “Se Vacancy Defects Coupling Effects in Mono-layer WSe2 Tunnel FETs”, Silicon Nanoelectronics Workshop(SNW), Hawaii, USA, June, 2018;

[9] X. Ma, Z. Fan, J. Wu, J. Chen, X. Jiang, “Channel Bending Effectson On/Off Currents in Mono-Layer MoS2 FETs”, Silicon Nanoelectronics Workshop(SNW), Hawaii, USA, June, 2018;

[10] W. Yang, J. Zhao, H. Cao, S. Chiu, J. Chen,“Oxide-Nitride-Oxide(ONO) Inter-poly Dielectric (IPD) Scaling Impacts on Data Retention Characteristics in NAND Flash Memories”, Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, June, 2018;

[11] J. Lu, Z. Fan, J. Gong, J. Chen, H. ManduLa, Y.Zhang, S. Yang and X. Jiang, “Enhancement of tunneling current in monolayer phosphorene tunnel field effect transistors by surface defects,” Physical Chemistry Chemical Physics, 20, pp.5699~5707, 2018.

[12] J. Wu, Z. Fan, J. Chen, X. Jiang, “Atomicdefects in monolayer WSe2 tunneling FETs studied by systematic ab initio calculations,” Applied Physics Express,11, 054001, 2018

[13] X. Shi, G. Xu, X. Duan, N. Lu, J. Chen, L. Li,M. Liu, “Analytical model of energy level alignment at metal-organic interface facilitating hole injection,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp.225-228, 2017.

[14] J. Wu, D. Han, W. Yang, S. Chen, X. Jiang, J.Chen, “Comprehensive Investigations on Charge Diffusion Physics in SiN-based 3DNAND Flash Memory through Systematical Ab initio Calculations,” IEDM Tech.Dig., San Francisco, CA, USA, p.4.5.1-4.5.4, 2017.

[15] J. Chen, J. Wu, X. Jiang, “Impacts of Traps onNano Scale Device Performance, Reliability, and Novel Applications”, invitedtalk, in International Microprocesses and Nanotechnology Conference, JeJu,Korea, November, 2017;

[16] H. Qiu, K. Takeuchi, T. Mizutani, T. Sarya, J.Chen, M. Kobayashi and T. Hitamoto. “Statistical Analyses of Random TelegraphNoise (RTN) Amplitude in Ultra-Narrow (Deep Sub-10nm) Silicon NanowireTransistors,” in Symposia on VLSI Technology, Kyoto, Japan, June, 2017.