Micro/Nano Device Reliability Laboratory

Publications (2017~)

[1]    J. Brown, R. Gao, J. Crowford, J. Wu, Z. Ji, J. Chen, J. Zhang, B. Zhou,B. Zhou, Q. Shi, W. Zhang, “A low-power and high-speed True Random NumberGenerator using generated RTN”, accepted by Symposia on VLSITechnology,Hawaii, USA, June, 2018;

[2]    J. Wu, X. Ma, J. Chen, X. Jiang, “Se Vacancy Defects Coupling Effects inMono-layer WSe2 Tunnel FETs”, accepted by IEEE Silicon Nanoelectronics Workshop(SNW), Hawaii, USA, June, 2018;

[3]    X. Ma, Z. Fan, J. Wu, J. Chen, X. Jiang, “Channel Bending Effects onOn/Off Currents in Mono-Layer MoS2 FETs”, accepted by IEEE SiliconNanoelectronics Workshop (SNW), Hawaii, USA, June, 2018;

[4]    W. Yang, J. Zhao, H. Cao, S. Chiu, J. Chen, “Oxide-Nitride-Oxide(ONO)Inter-poly Dielectric (IPD) Scaling Impacts on Data Retention Characteristicsin NAND Flash Memories”, accepted by IEEE Silicon Nanoelectronics Workshop (SNW),Hawaii, USA, June, 2018;

[5]    J. Lu, Z. Fan, J. Gong, J. Chen, H. ManduLa, Y. Zhang, S. Yang and X. Jiang,Enhancement of tunneling current in monolayer phosphorenetunnel field effect transistors by surface defects, Physical Chemistry Chemical Physics, 20, pp.5699~5707,2018;

[6]    J. Wu, Z. Fan, J. Chen, X. Jiang, “Atomic defects in monolayer WSe2tunneling FETs studied by systematic ab initio calculations”, Applied PhysicsExpress 11, 054001, 2018;

[7]    X. Shi, G. Xu, X. Duan, N. Lu, J. Chen, L. Li, M. Liu, “Analytical modelof energy level alignment at metal-organic interface facilitating holeinjection,” International Conference on Simulation of Semiconductor Processesand Devices (SISPAD), pp.225-228, 2017;

[8]    J. Wu, D. Han, W. Yang, S. Chen, X. Jiang, J. Chen, “Comprehensive Investigations on Charge DiffusionPhysics in SiN-based 3D NAND Flash Memory through Systematical Ab initioCalculations,” IEDM Tech. Dig.,San Francisco, CA, USA, p.4.5.1-4.5.4, 2017;

[9]    J. Chen, J. Wu, X. Jiang, “Impacts of Traps on Nano Scale DevicePerformance, Reliability, and Novel Applications”, invited talk, InternationalMicroprocesses and Nanotechnology Conference, JeJu, Korea, November, 2017;

[10]H. Qiu, K. Takeuchi, T. Mizutani, T. Sarya, J. Chen,M. Kobayashi and T. Hitamoto. “Statistical Analyses of Random Telegraph Noise(RTN) Amplitude in Ultra-Narrow (Deep Sub-10nm) Silicon Nanowire Transistors,”in Symposia on VLSITechnology, Kyoto, Japan, June,2017.

[11]J. Chen, “On the Reliability in 3D NAND FlashMemories”, invited talk, 2017 International Workshop on Reliability of Micro-and Nano-Electronic Devices in Harsh Environment, Sichuan, China, May, 2017;

[12]J. Chen,” Random Telegraph Signal Noise in SiMOSFETs and High-k MISFETs”, invited talk, IUMRS International Conference inAsia, Qingdao, China, October, 2016;

Selected Publications (~ 2016)

[1]    J. Chen, Y. Nakasaki and Y. Mitani. “Deep Insight into Process-inducedPre-existing Traps and PBTI Stress-induced Trap Generations in High-k GateDielectrics through Systematic RTN Characterizations and Ab initioCalculations,” in Symposia onVLSITechnology, Hawaii,USA, June, 2016.

[2]    J. Chen, T. Tanamoto, H. Noguchi and Y. Mitani. “Further Investigations onTraps Stabilities in Random Telegraph Signal Noise and the Application to aNovel Concept Physical Unclonable Function (PUF) with Robust Reliabilities,” inSymposia on VLSI Technology,Kyoto, Japan, June, 2015.

[3]    J. Chen, Y. Higashi, K. Kato and Y. Mitani. “Further Understandings onRandom Telegraph Signal Noise through Comprehensive Studies on Large TimeConstant Variations and its Strong Correlations to Thermal ActivationEnergies,” in Symposium on VLSITechnology, Hawaii, USA, June, 2014.

[4]    J. Chen, Y. Higashi, I. Hirano, and Y. Mitani. “Understanding of ChannelDoping Concentration Impacts on Random Telegraph Signal Noise and SuccessfulNoise Suppression from Strain Induced Mobility Enhancement,” in Symposium on VLSI Technology, Kyoto,Japan, June, 2013.

[5]    J. Chen, I. Hirano, K. Tatsumura and Y. Mitani. “ComprehensiveInvestigations on Neutral and Attractive Traps in Random Telegraph Signal NoisePhenomena using (100)- and (110)-Orientated CMOSFETs,” in Symposium on VLSI Technology,Hawaii, USA, June, 2012.

[6]    J. Chen, T. Saraya, T. Hiramoto. “Mobility enhancement over universalmobility in (100) silicon nanowire gate-all-around MOSFETs with width andheight of less than 10nm range,” in Symposiumon VLSI Technology, Hawaii, USA, p.175, 2010.

[7]    J. Chen, T. Saraya, T. Hiramoto. “High Hole Mobility in Multiple SiliconNanowire Gate-All-Around pMOSFETs on (110) SOI,” inSymposium on VLSI Technology, Kyoto, Japan, June, 2009.

[8]    J. Chen, T. Saraya, K. Miyaji, K. Shimizu, T. Hiramoto. ” ExperimentalStudy of Mobility in [110]- and [100]-Directed Multiple Silicon Nanowire GAAMOSFETs on (100) SOI,” in Symposium onVLSI Technology, Hawaii, USA, p.93, 2008.

[9]    J. Chen, T. Saraya, K. Miyaji, K. Shimizu, T. Hiramoto. ”ExperimentalStudy of Mobility in [110]- and [100]-Directed Multiple Silicon Nanowire GAAMOSFETs on (100) SOI,” in Symposium onVLSI Technology, Hawaii, USA, p.93, 2008.

[10]J. Chen, T. Saraya, T. Hiramoto. “Electron Mobilityin Multiple Silicon Nanowires GAA nMOSFETs on (110) and (100) SOI at Room andLow Temperature,” in IEDM Tech. Dig.,San Francisco, CA, USA, p.757, 2008.

[11]Y. Jeong, J. Chen, T. Saraya, T. Hiramoto. “UniaxialStrain Effects on Silicon Nanowire pMOSFET and Single-Hole Transistor at RoomTemperature,” in IEDM Tech. Dig.,San Francisco, CA, p.761, 2008.